1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly, to a method of fabricating a silicon nitride film on a substrate.
2. Description of the Related Art
Scaling of field effect transistor devices has historically been, and continues to be a fundamental goal in the semiconductor fabrication industry. The continual drive toward higher circuit density has been fueled by demands from ordinary consumers, industry, government and the military for ever increasing speed, capability and miniaturization of electronic products, as well as the desire of semiconductor manufacturers to reduce manufacturing costs. Scaling efforts have thus far been highly successful. Three micron processing, considered state of the art a little more than a decade ago, has given way to sub-micron processing.
As in many aspects of semiconductor processing, current scaling efforts involve a set of trade-offs between higher packing density and better performance, and short channel effects. As process technologies scaled below about 2.0 .mu.m, a series of design difficulties arose stemming from the semiconductor physics associated with short-channel devices. Hot carrier effects and subthreshold leakage currents become much more problematic in short channel devices, such as modem field effect transistors in sub-2.0 .mu.m processing. If not compensated for through processing techniques or other means, such effects can either reduce device performance or lead to device failure or both.
One technique to combat short channel effects has involved the scaling of gate dielectrics. To compensate for the potentially lower drive currents for a given short channel device, conventional silicon dioxide gate oxide layers are made as thin as possible to maximize drive current. However, the scaling of silicon dioxide gate dielectric layers has introduced another set of problems. To begin with, very thin silicon dioxide layers have been historically difficult to fabricate with a consistent thickness across a given wafer, from wafer to wafer and from lot to lot. In addition, as the thickness of silicon dioxide is scaled downward, the potential for reliability problems associated with dielectric breakdown and hot and cold carrier injection degradation increases. Hot and cold carrier degradation can significantly reduce device performance, while dielectric breakdown can lead to complete device failure.
One potential cause of carrier injection and potential dielectric breakdown is thought to occur as a result of interface traps near the Si--SiO.sub.2 interface. Interface traps are the apparent result of dangling silicon bonds at the Si--SiO.sub.2 interface. Dangling Si bonds represent sites where hot carrier injection, Fowler-Nordheim tunneling and direct tunneling can occur. Although tunneling is thought to arise as a natural consequence of the quantum mechanical nature of electrons positioned near a very thin oxide layer, dangling Si bonds appear to aggravate the problem. Independent of the exact physical cause of carrier injection, the empirical result for very thin oxides may be gate leakage currents and/or catastrophic device failure.
Another difficulty associated with very thin conventional gate oxides is polysilicon depletion. In p-channel transistors with polysilicon gate electrodes, the source and drain are commonly formed in the substrate by implanting a p-type dopant, such as boron. The implant also deposits boron into the polysilicon of the gate electrode. Subsequent thermal processing steps to fabricate a conventional p-channel field effect transistor frequently cause boron to diffuse from the gate electrode through the gate oxide layer and into the channel region. If the amount of boron diffused is sufficiently high, the electrical performance of the field effect transistor may be severely degraded due to polysilicon depletion. The potential for boron diffusion increases with decreasing oxide thickness.
Silicon nitride has been previously proposed as an alternative to silicon dioxide as a gate dielectric material. With a dielectric constant of about 6-9 (nearly twice that of silicon dioxide) a silicon nitride gate dielectric may be fabricated with a greater thickness than a comparable oxide layer while still achieving the same capacitance per unit area. The result is better resistance to tunneling effects and dielectric breakdown without sacrificing drive current. Silicon nitride also is more resistant to diffusion and thus to polysilicon depletion.
Low pressure chemical vapor deposition ("LPCVD") and plasma enhanced chemical vapor deposition ("PECVD") represent two commonly used techniques for depositing silicon nitride films. LPCVD silicon nitride is usually formed by reacting dichlorosilane and ammonia at temperatures above 700.degree. C. Such films have relatively high tensile stresses (on the order of about 1-2.times.10.sup.10 dynes/cm.sup.2), and the high temperature required for their fabrication consumes thermal budget. Furthermore, adequate control of film thickness uniformity for thicknesses under about 50 .ANG. has proven to be difficult.
PECVD silicon nitride is usually formed by reacting silane and ammonia in a plasma ambient at about 200 to 400.degree. C. These types of silicon nitride films frequently exhibit mechanical stresses that are compressive and an order of magnitude lower than LPCVD silicon nitride films. Film thickness uniformity is generally more controllable in PECVD processes than in LPCVD processes. However, in the regimen of film thicknesses less than about 50 .ANG., conventional PECVD silicon nitride deposition processes also produce variations in film thickness. The problem is thought to stem from the high silane flow rates and the sequence of plasma excitation and silane flow used in current processes. Higher silane flow rates generally speed the silicon nitride forming reaction and make the task of thickness control more difficult. Some conventional processes excite the plasma prior to the introduction of silane into the reaction chamber. Exciting the plasma prior to silane flow can cause the resulting silane-ammonia plasma to exhibit instability, which produces variations in film thickness.
Some conventional processes have utilized a composite thermal oxide-silicon nitride stack as a gate dielectric. A thermal oxide film is first grown on the silicon wafer. A silicon nitride film is next deposited on the oxide. The aforementioned process limitations associated with nitride films apply in this context as well. Furthermore, the conventional gate oxide growth process used to fabricate these types of composite layers is not self-limiting and thus somewhat difficult to control, particularly where very thin oxides are required.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.